? semiconductor components industries, llc, 2011 october, 2011 ? rev. 3 1 publication order number: NTMD4N03R2/d NTMD4N03R2, nvmd4n03r2 power mosfet 4 amps, 30 volts n ? channel so ? 8 dual features ? designed for use in low voltage, high speed switching applications ? ultra low on ? resistance provides higher efficiency and extends battery life ? r ds(on) = 0.048 , v gs = 10 v (typ) ? r ds(on) = 0.065 , v gs = 4.5 v (typ) ? miniature so ? 8 surface mount package ? saves board space ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? aec q101 qualified ? nvmd4n03r2 ? these devices are pb ? free and are rohs compliant applications ? dc ? dc converters ? computers ? printers ? cellular and cordless phones ? disk drives and tape drives maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage ? continuous v gs 20 v drain current ? continuous @ t a = 25 c ? single pulse (tp 10 s) i d i dm 4.0 12 adc apk total power dissipation @ t a = 25 c (note 1) p d 2.0 w operating and storage temperature range t j , t stg ? 55 to +150 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, peak i l = 4.45 apk, l = 8 mh, r g = 25 ) e as 80 mj thermal resistance ? junction ? to ? ambient (note 1) r ja 62.5 c/w maximum lead temperature for soldering purposes for 10 seconds t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. when surface mounted to an fr4 board using 1 pad size, t 10 s n ? channel http://onsemi.com v dss r ds(on) typ i d max 30 v 48 m @ v gs = 10 v 4.0 a soic ? 8 suffix nb case 751 style 11 marking diagram * and pin assignment e4n03 = specific device code a = assembly location y = year ww = work week = pb ? free package e4n03 ayww 1 8 1 8 s1 g1 s2 g2 d1 d1 d2 d2 *for additional marking information, refer to application note and8002/d. (note: microdot may be in either location) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d device package shipping ? ordering information NTMD4N03R2g soic ? 8 (pb ? free) 2500 / tape & reel d s g d s g nvmd4n03r2g soic ? 8 (pb ? free) 2500 / tape & reel
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (v gs = 0 vdc, i d = 250 a) temperature coefficient (positive) v (br)dss 30 ? ? 32 ? ? vdc mv/ c zero gate voltage drain current (v ds = 30 vdc, v gs = 0 vdc, t j = 25 c) (v ds = 30 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 1.0 10 adc gate ? body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 2) gate threshold voltage (v ds = v gs , i d = 250 adc) temperature coefficient (negative) v gs(th) 1.0 ? 1.9 4.2 3.0 ? vdc mv/ c static drain ? to ? source on ? state resistance (v gs = 10 vdc, i d = 4 adc) (v gs = 4.5 vdc, i d = 2 adc) r ds(on) ? ? 0.048 0.065 0.060 0.080 forward transconductance (v ds = 3 vdc, i d = 2 adc) g fs ? 6.0 ? mhos dynamic characteristics input capacitance (v ds = 20 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 285 400 pf output capacitance c oss ? 95 135 reverse transfer capacitance c rss ? 35 70 switching characteristics (notes 2 & 3) turn ? on delay time (v dd = 20 vdc, i d = 2 a, v gs = 10 v, r g = 2 ) t d(on) ? 7.0 15 ns rise time t r ? 14 30 turn ? off delay time t d(off) ? 16 30 fall time t f ? 10 20 gate charge (v ds = 10 vdc, v gs = 10 vdc, i d = 3.5 a) q t ? 8.0 16 nc q 1 ? 1.1 ? q 2 ? 1.9 ? body ? drain diode ratings (note 2) diode forward on ? voltage (i s = 2 adc, v gs = 0 v) (i s = 2 adc, v gs = 0 v, t j = 150 c) v sd ? ? 0.82 0.63 1.0 ? vdc reverse recovery time (i s = 2 a, v gs = 0 v, di s /dt = 100 a/ s) t rr ? 14 ? ns t a ? 10 ? t b ? 4.0 ? reverse recovery stored charge (i s = 2 a, di s /dt = 100 a/ s, v gs = 0 v) q rr ? 0.008 ? c 2. pulse test: pulse width 300 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperature.
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 3 typical mosfet electrical characteristics 1.5 1.375 0.875 1.125 0.75 100 10 10,000 0 1.0 4 0.2 v ds , drain ? to ? source voltage (volts) i d , drain current (amps) 0 v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 2 0.075 0.05 7 6 5 0.025 0 8 figure 3. on ? resistance versus drain current and temperature i d , drain current (amps) figure 4. on ? resistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current versus voltage v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) ? 50 0 ? 25 50 25 04 2 15 01520 10 30 5 2 6 8 v ds 10 v t j = 25 c t j = ? 55 c t j = 125 c 150 i d = 2 a v gs = 10 v 0.10 v gs = 3 v v gs = 10 0.6 5 2 0 1 3 4 7 0.04 0.06 6 5 4 0.02 0 3 0.10 1000 t j = 25 c t j = 25 c 0.4 0.8 10 v 8 v 4 v 3.6 v 3 34 t = 125 c t = ? 55 c t = 25 c 28 7 v gs = 4.5 v v gs = 10 v 1 100 75 125 1.25 25 v gs = 0 v t j = 150 c t j = 125 c 4.5 v 5 v 6 v 6 0.08
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. figure 7. capacitance variation 10 15 20 10 5 50 25 800 600 400 200 0 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) c rss c iss c oss c rss t j = 25 c v ds = 0 v v gs v ds v gs = 0 v c iss
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 5 figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge figure 9. resistive switching time variation versus gate resistance i d = 4 a t j = 25 c v gs q 2 q 1 q t v ds 30 0 20 10 6 0 q g , total gate charge (nc) v gs , gate ? to ? source voltage (volts) 04 8 10 8 4 2 123 567 100 1 r g , gate resistance ( ) t, time (ns) 1 100 10 10 v dd = 15 v i d = 4 a v gs = 10 v t r t d(off) t d(on) t f 910 v ds , drain ? to ? source voltage (volts) drain ? to ? source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 14. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode?s negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 4 2 0 figure 10. diode forward voltage versus current v sd , source ? to ? drain voltage (volts) i s , source current (amps) 0.5 0.6 v gs = 0 v t j = 25 c 0.7 0.8 0.9 1 3
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 6 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions dif fering from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. figure 11. maximum rated forward biased safe operating area 0.1 v ds , drain ? to ? source voltage (volts) 1 10 r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c 10 0.01 dc 10 ms 1.0 100 100 1.0 ms 0.1 figure 12. maximum avalanche energy versus starting junction temperature 80 0 t j , starting junction temperature ( c) e as , single pulse drain ? to ? source avalanche energy (mj) 25 125 150 100 75 50 60 i d = 4.45 a 20 40 i d , drain current (amps)
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 7 typical electrical characteristics figure 13. thermal response figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b t, time (s) rthja(t), effective transient thermal resistance 1.0 0.1 0.01 d = 0.5 single pulse 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.001 chip junction 0.0106 0.0253 f 0.0431 0.1406 f 0.1643 0.5064 f 0.3507 2.9468 f 0.4302 177.14 f ambient
NTMD4N03R2, nvmd4n03r2 http://onsemi.com 8 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 11: pin 1. source 1 2. gate 1 3. source 2 4. gate 2 5. drain 2 6. drain 2 7. drain 1 8. drain 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NTMD4N03R2/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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